A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Split manufacturing (SM) and layout camouflaging (LC) are two promising techniques to obscure integrated circuits (ICs) from malicious entities during after manufacturing. While both enable protecting the intellectual property (IP) of ICs, SM can further mitigate insertion hardware Trojans (HTs). In this paper, we strive for "best worlds," that is seek combine individual strengths LC. By jointly extending LC toward 3D integration, an up-and-coming paradigm based on stacking interconnecting multiple chips, establish a modern approach security. Toward end, develop security-driven CAD flow ICs in variations, one IP protection HT prevention. Essential concepts (i) "3D splitting" netlist protect, (ii) obfuscation vertical interconnects (i.e., wiring between stacked chips), (iii) prevention, synthesis stage. We conduct comprehensive experiments DRC-clean layouts multi-million-gate DARPA OpenCores designs (and others). Strengthened by extensive security analysis argue entering third dimension eminent effective efficient